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ASIC Design Verification Engineer salaries

Pay ranges employers published in 90 open job postings for ASIC Design Verification Engineer roles at 19 companies, updated Nov 14, 2026.

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Posted base pay ranges from job listings, not total compensation. Figures are in USD; 6 more postings in CAD (median CA$155K). How these figures are made

Pay distribution

ASIC Design Verification Engineer: postings by posted pay84 postings by the midpoint of their pay range, in 10 bands from $140K to $340K. Median $213K; middle half $168K–$238K.Median $213K$140K$340K

Postings per pay band: $140K–$160K: 9; $160K–$180K: 14; $180K–$200K: 5; $200K–$220K: 28; $220K–$240K: 9; $240K–$260K: 1; $260K–$280K: 11; $280K–$300K: 0; $300K–$320K: 0; $320K–$340K: 7.

Pay by level

  1. Entry level$133K median, $133K–$146K typical, 4 postingsEntry level: middle half $133K–$146K, median $133K
  2. Mid level$168K median, $167K–$203K typical, 30 postingsMid level: middle half $167K–$203K, median $168K
  3. Senior$213K median, $207K–$231K typical, 36 postingsSenior: middle half $207K–$231K, median $213K
  4. Staff$238K median, $238K–$267K typical, 5 postingsStaff: middle half $238K–$267K, median $238K
  5. Principal$323K median, $323K–$323K typical, 9 postingsPrincipal: middle half $323K–$323K, median $323K

Companies hiring

  1. Cisco$203K median, $189K–$207K typical, 14 postingsCisco: middle half $189K–$207K, median $203K
  2. Blue Origin$323K median, $277K–$323K typical, 13 postingsBlue Origin: middle half $277K–$323K, median $323K
  3. HPE$206K median, $167K–$213K typical, 12 postingsHPE: middle half $167K–$213K, median $206K
  4. Qualcomm$168K median, $155K–$238K typical, 10 postingsQualcomm: middle half $155K–$238K, median $168K

Top-paying companies

  1. Blue Origin · $323K median, 13 postings
  2. Positron · $275K median, 3 postings
  3. Hewlett Packard Enterprise · $213K median, 5 postings
  4. SpaceX · $213K median, 3 postings

By location

  1. United States$213K median, $169K–$238K typical, 81 postingsUnited States: middle half $169K–$238K, median $213K
  2. California$207K median, $168K–$238K typical, 40 postingsCalifornia: middle half $168K–$238K, median $207K
  3. San Jose, CA$203K median, $189K–$207K typical, 14 postingsSan Jose, CA: middle half $189K–$207K, median $203K
  4. Santa Clara, CA$168K median, $168K–$238K typical, 10 postingsSanta Clara, CA: middle half $168K–$238K, median $168K
  5. Remote$277K median, $238K–$323K typical, 16 postingsRemote: middle half $238K–$323K, median $277K

Remote vs on-site

Remote: $277K median, $238K–$323K typical, from 15 postings. On-site: $207K median, $168K–$218K typical, from 40 postings.

Newest ASIC Design Verification Engineer postings

  1. Senior ASIC Design Verification EngineerK2 Space · Remote · $170K–$250K/yr · Posted Nov 12, 2026Apply
  2. Principal ASIC Design Verification EngineerK2 Space · Remote · $190K–$285K/yr · Posted Nov 12, 2026Apply
  3. Senior ASIC Design Verification EngineerPositron AI · Remote · $200K–$350K/yr · Posted Nov 12, 2026
  4. ASIC Design Verification EngineerCisco · San Jose, CA · $155K–$223K/yr · Posted Nov 5, 2026
  5. ASIC Design Verification EngineerMeta · United States · $178K–$250K/yr · Posted Nov 5, 2026
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Questions and answers

How much does a ASIC Design Verification Engineer make?

The median posted base pay for ASIC Design Verification Engineer jobs is $213K a year, from 90 job postings with pay at 19 companies.

What is the typical ASIC Design Verification Engineer pay range?

The middle half of postings list $168K–$238K. The top 10% list $277K a year or more, and the lowest 10% $155K or less.

Which companies pay the most for ASIC Design Verification Engineer jobs?

By median posted pay: Blue Origin ($323K), Positron ($275K), Hewlett Packard Enterprise ($213K).

How does ASIC Design Verification Engineer pay change with level?

Median posted pay by level read from job titles: Entry level $133K, Mid level $168K, Senior $213K, Staff $238K, Principal $323K.

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