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ASIC Design Verification Engineer salaries in Santa Clara, CA

Pay ranges employers published in 10 open job postings for ASIC Design Verification Engineer roles in Santa Clara, CA, updated Nov 14, 2026.

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Posted base pay ranges from job listings, not total compensation. Figures are in USD. How these figures are made

Newest ASIC Design Verification Engineer postings in Santa Clara, CA

  1. ASIC Design Verification Engineer (Security Group) - Sr StaffQualcomm · Santa Clara, CA · $190K–$285K/yr · Posted Oct 25, 2026
  2. ASIC Design Verification Engineer (Security Group) - Sr StaffQualcomm · Santa Clara, CA · $190K–$285K/yr · Posted Oct 24, 2026
  3. ASIC Design Verification Engineer (Security Group) - Sr StaffSanta Clara, CA · $190K–$285K/yr · Posted Oct 24, 2026
  4. Senior ASIC Design Verification EngineerPalo Alto Networks · Santa Clara, CA · $129K–$209K/yr · Posted Oct 20, 2026
  5. ASIC Design Verification Engineer (Santa Clara, CA)Qualcomm · Santa Clara, CA · $134K–$202K/yr · Posted Oct 17, 2026
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ASIC Design Verification Engineer pay in other places

  1. United States$213K median, $169K–$238K typical, 81 postingsUnited States: middle half $169K–$238K, median $213K
  2. California$207K median, $168K–$238K typical, 40 postingsCalifornia: middle half $168K–$238K, median $207K
  3. San Jose, CA$203K median, $189K–$207K typical, 14 postingsSan Jose, CA: middle half $189K–$207K, median $203K
  4. CanadaCA$155K median, CA$155K–CA$155K typical, 9 postings
  5. Ontario, CanadaCA$155K median, CA$155K–CA$155K typical, 7 postings
  6. Markham, ON, CanadaCA$155K median, CA$155K–CA$155K typical, 7 postings
  7. Los Angeles, CA$277K median, $277K–$323K typical, 5 postingsLos Angeles, CA: middle half $277K–$323K, median $277K
  8. Texas$275K median, $167K–$275K typical, 5 postingsTexas: middle half $167K–$275K, median $275K

All ASIC Design Verification Engineer salaries

Questions and answers

How much does a ASIC Design Verification Engineer make in Santa Clara, CA?

The median posted base pay for ASIC Design Verification Engineer jobs in Santa Clara, CA is $168K a year, from 10 job postings with pay at 2 companies.

What is the typical ASIC Design Verification Engineer pay range in Santa Clara, CA?

The middle half of postings list $168K–$238K. The top 10% list $238K a year or more, and the lowest 10% $141K or less.

How does Santa Clara, CA pay compare with all ASIC Design Verification Engineer jobs?

The median here is $168K, against $213K across all 90 postings for the role.

How many ASIC Design Verification Engineer jobs in Santa Clara, CA list pay?

10 open postings at 2 companies list a pay range; figures use postings with at least 3 per group.

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