Skip to content
applystead.Get started

APPLYSTEAD SALARIES · 5 POSTED PAY RANGES

FPGA Design Verification Engineer salaries

Pay ranges employers published in 5 open job postings for FPGA Design Verification Engineer roles at 2 companies, updated Oct 18, 2026.

Continue with GoogleGet matched to FPGA Design Verification Engineer jobs

Posted base pay ranges from job listings, not total compensation. Figures are in USD. How these figures are made

Pay distribution

FPGA Design Verification Engineer: postings by posted pay5 postings by the midpoint of their pay range, in 10 bands from $60.00/hr to $110.00/hr. Median $62.50/hr ($130K/yr); middle half $62.50–$62.50/hr.Median $62.50/hr$60.00/hr$110.00/hr

Postings per pay band: $60.00/hr–$65.00/hr: 4; $65.00/hr–$70.00/hr: 0; $70.00/hr–$75.00/hr: 0; $75.00/hr–$80.00/hr: 0; $80.00/hr–$85.00/hr: 0; $85.00/hr–$90.00/hr: 0; $90.00/hr–$95.00/hr: 0; $95.00/hr–$100.00/hr: 0; $100.00/hr–$105.00/hr: 0; $105.00/hr–$110.00/hr: 1.

Pay by level

  1. Mid level$62.50/hr ($130K/yr) median · $62.50–$62.50/hr typical · 5 postingsMid level: middle half $62.50–$62.50/hr, median $62.50/hr ($130K/yr)

Companies hiring

  1. Inabia$62.50/hr ($130K/yr) median · $62.50–$62.50/hr typical · 3 postingsInabia: middle half $62.50–$62.50/hr, median $62.50/hr ($130K/yr)
  2. UST2 postings · too few to show pay

Top-paying companies

  1. Inabia · $130K median · 3 postings

By location

  1. United States$62.50/hr ($130K/yr) median · $62.50–$62.50/hr typical · 5 postingsUnited States: middle half $62.50–$62.50/hr, median $62.50/hr ($130K/yr)
  2. California$62.50/hr ($130K/yr) median · $62.50–$62.50/hr typical · 5 postingsCalifornia: middle half $62.50–$62.50/hr, median $62.50/hr ($130K/yr)
  3. El Segundo, CA$62.50/hr ($130K/yr) median · $62.50–$62.50/hr typical · 3 postingsEl Segundo, CA: middle half $62.50–$62.50/hr, median $62.50/hr ($130K/yr)

Remote vs on-site

Remote: too few postings list pay to show a figure. On-site: $62.50/hr ($130K/yr) median, $62.50–$62.50/hr typical, from 5 postings.

Newest FPGA Design Verification Engineer postings

  1. FPGA Design Verification EngineerInabia · El Segundo, CA · $60.00–$65.00/hr · Posted Oct 18, 2026Apply
  2. FPGA Design Verification EngineerInabia · El Segundo, CA · $60.00–$65.00/hr · Posted Oct 18, 2026Apply
  3. FPGA Design Verification EngineerInabia · El Segundo, CA · $60.00–$65.00/hr · Posted Oct 18, 2026Apply
  4. FPGA Design Verification EngineerUST · Mountain View, CA · $101K–$152K/yr · Posted Oct 17, 2026
  5. FPGA Design Verification EngineerUST · Mountain View, CA · $182K–$273K/yr · Posted Oct 17, 2026
  6. Want Applystead to find more jobs like these? Start free trial →

Software EngineerElectrical EngineerSystems EngineerMechanical EngineerProject Engineer

Questions and answers

How much does a FPGA Design Verification Engineer make?

The median posted base pay for FPGA Design Verification Engineer jobs is $62.50/hr ($130K/yr), from 5 job postings with pay at 2 companies.

What is the typical FPGA Design Verification Engineer pay range?

The middle half of postings list $62.50–$62.50/hr. The top 10% list $228K a year or more, and the lowest 10% $127K or less.

Which companies pay the most for FPGA Design Verification Engineer jobs?

By median posted pay: Inabia ($130K).

Free tools and comparisons

Applystead vs AIApplyApplystead vs ApplyBlastSTAR method answer generatorTell me about yourself answer generatorTotal compensation calculatorTwo weeks notice letter generator

Get matched to FPGA Design Verification Engineer jobs · Start free trial