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APPLYSTEAD SALARIES · 2 POSTED PAY RANGES

UST FPGA Design Verification Engineer salaries

Pay ranges UST published in 2 open job postings for FPGA Design Verification Engineer roles, updated Oct 18, 2026.

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Postings with pay2

Fewer than 3 postings here list pay, so no pay figures are shown.

Posted base pay ranges from job listings, not total compensation. How these figures are made

Locations

United States · 2 postings
California · 2 postings
Mountain View, CA · 2 postings

Newest UST FPGA Design Verification Engineer postings

FPGA Design Verification EngineerUST · Mountain View, CA · $101K–$152K/yr · Posted Oct 17, 2026
FPGA Design Verification EngineerUST · Mountain View, CA · $182K–$273K/yr · Posted Oct 17, 2026
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