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APPLYSTEAD SALARIES · 2 POSTED PAY RANGES

Celero Communications ASIC Design Engineer salaries

Pay ranges Celero Communications published in 2 open job postings for ASIC Design Engineer roles, updated Oct 18, 2026.

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Fewer than 3 postings here list pay, so no pay figures are shown.

Posted base pay ranges from job listings, not total compensation. How these figures are made

Locations

  1. United States · 2 postings
  2. California · 2 postings
  3. San Jose, CA · 1 posting
  4. Irvine, CA · 1 posting

Newest Celero Communications ASIC Design Engineer postings

  1. ASIC Design Engineer - Digital DSP Design & Analog/Mixed-SignalCelero Communications · Irvine, CA · $150K–$250K/yr · Posted Oct 18, 2026Apply
  2. ASIC Design Engineer - Digital DSP Design & Analog/Mixed-SignalCelero Communications · San Jose, CA · $150K–$250K/yr · Posted Oct 18, 2026Apply
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