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APPLYSTEAD SALARIES · 4 POSTED PAY RANGES

Teradynein FPGA Design Engineer salaries

Pay ranges Teradynein published in 4 open job postings for FPGA Design Engineer roles, updated Oct 11, 2026.

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Posted base pay ranges from job listings, not total compensation. Figures are in USD. How these figures are made

Locations

  1. United States · $176K median · 4 postings
  2. California · 2 postings
  3. San Jose, CA · 2 postings
  4. Oregon · 2 postings
  5. Tualatin, OR · 2 postings

Newest Teradynein FPGA Design Engineer postings

  1. Senior FPGA Design Engineer (MTD, Tualatin, OR)Teradynein · Tualatin, OR · $155K–$248K/yr · Posted Oct 10, 2026
  2. Senior FPGA Design Engineer (MTD, San Jose, CA)Teradynein · San Jose, CA · $170K–$273K/yr · Posted Oct 10, 2026
  3. FPGA Design Engineer (MTD, San Jose, CA)Teradynein · San Jose, CA · $135K–$217K/yr · Posted Oct 10, 2026
  4. FPGA Design Engineer (MTD, Tualatin, OR)Teradynein · Tualatin, OR · $123K–$197K/yr · Posted Oct 10, 2026
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