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APPLYSTEAD SALARIES · 10 POSTED PAY RANGES

ASIC / FPGA Design Verification Engineer salaries

Pay ranges employers published in 10 open job postings for ASIC / FPGA Design Verification Engineer roles at 1 company, updated Oct 4, 2026.

Posted base pay ranges from job listings, not total compensation. Figures are in USD. How these figures are made

Pay distribution

ASIC / FPGA Design Verification Engineer: postings by posted pay10 postings by the midpoint of their pay range, in 12 bands from $115K to $175K. Median $116K; middle half $116K–$172K.Median $116K$115K$175K

Postings per pay band: $115K–$120K: 6; $120K–$125K: 0; $125K–$130K: 0; $130K–$135K: 0; $135K–$140K: 0; $140K–$145K: 0; $145K–$150K: 0; $150K–$155K: 0; $155K–$160K: 0; $160K–$165K: 0; $165K–$170K: 0; $170K–$175K: 4.

Pay by level

  1. Entry level$116K median · $116K–$116K typical · 6 postingsEntry level: middle half $116K–$116K, median $116K
  2. Senior$172K median · $172K–$172K typical · 4 postingsSenior: middle half $172K–$172K, median $172K

Companies hiring

  1. Boeing$116K median · $116K–$172K typical · 10 postingsBoeing: middle half $116K–$172K, median $116K

Top-paying companies

  1. Boeing · $116K median · 10 postings

By location

  1. United States$116K median · $116K–$172K typical · 10 postingsUnited States: middle half $116K–$172K, median $116K

Remote vs on-site

Remote: too few postings list pay to show a figure. On-site: $116K median, $116K–$172K typical, from 9 postings.

Newest ASIC / FPGA Design Verification Engineer postings

  1. ASIC / FPGA Design Verification Engineer - (Associate or Experienced)Boeing · El Segundo, CA · $98.6K–$133K/yr · Posted Sep 26, 2026ApplyView posting
  2. ASIC / FPGA Design Verification Engineer - (Associate or Experienced)Boeing · United States · $98.6K–$133K/yr · Posted Sep 26, 2026ApplyView posting
  3. ASIC / FPGA Design Verification Engineer - (Associate or Experienced)Boeing · United States · $98.6K–$133K/yr · Posted Aug 26, 2026ApplyView posting
  4. ASIC / FPGA Design Verification Engineer - (Associate or Experienced)Boeing · United States · $98.6K–$133K/yr · Posted Aug 26, 2026ApplyView posting
  5. ASIC / FPGA Design Verification Engineer – (Lead or Senior)Boeing · United States · $146K–$198K/yr · Posted Aug 23, 2026ApplyView posting
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Questions and answers

How much does a ASIC / FPGA Design Verification Engineer make?

The median posted base pay for ASIC / FPGA Design Verification Engineer jobs is $116K a year, from 10 job postings with pay at 1 company.

What is the typical ASIC / FPGA Design Verification Engineer pay range?

The middle half of postings list $116K–$172K. The top 10% list $172K a year or more, and the lowest 10% $116K or less.

Which companies pay the most for ASIC / FPGA Design Verification Engineer jobs?

By median posted pay: Boeing ($116K).

How does ASIC / FPGA Design Verification Engineer pay change with level?

Median posted pay by level read from job titles: Entry level $116K, Senior $172K.

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