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APPLYSTEAD SALARIES · 10 POSTED PAY RANGES

Boeing ASIC / FPGA Design Verification Engineer salaries

Pay ranges Boeing published in 10 open job postings for ASIC / FPGA Design Verification Engineer roles, updated Oct 4, 2026.

Posted base pay ranges from job listings, not total compensation. Figures are in USD. How these figures are made

Boeing’s ASIC / FPGA Design Verification Engineer titles

  1. ASIC / FPGA Design Verification Engineer (Entry level)$116K median · $116K–$172K typical · 10 postingsASIC / FPGA Design Verification Engineer (Entry level): middle half $116K–$172K, median $116K

Pay by level

  1. Entry level$116K median · $116K–$116K typical · 6 postingsEntry level: middle half $116K–$116K, median $116K
  2. Senior$172K median · $172K–$172K typical · 4 postingsSenior: middle half $172K–$172K, median $172K

Locations

  1. United States · $116K median · 10 postings
  2. California · 1 posting
  3. El Segundo, CA · 1 posting

Newest Boeing ASIC / FPGA Design Verification Engineer postings

  1. ASIC / FPGA Design Verification Engineer - (Associate or Experienced)Boeing · El Segundo, CA · $98.6K–$133K/yr · Posted Sep 26, 2026ApplyView posting
  2. ASIC / FPGA Design Verification Engineer - (Associate or Experienced)Boeing · United States · $98.6K–$133K/yr · Posted Sep 26, 2026ApplyView posting
  3. ASIC / FPGA Design Verification Engineer - (Associate or Experienced)Boeing · United States · $98.6K–$133K/yr · Posted Aug 26, 2026ApplyView posting
  4. ASIC / FPGA Design Verification Engineer - (Associate or Experienced)Boeing · United States · $98.6K–$133K/yr · Posted Aug 26, 2026ApplyView posting
  5. ASIC / FPGA Design Verification Engineer – (Lead or Senior)Boeing · United States · $146K–$198K/yr · Posted Aug 23, 2026ApplyView posting
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