APPLYSTEAD SALARIES · 9 POSTED PAY RANGES
Boeing ASIC/FPGA Design and Verification Engineer salaries
Pay ranges Boeing published in 9 open job postings for ASIC/FPGA Design and Verification Engineer roles, updated Oct 4, 2026.
- Median base pay$161,000a year
- Typical range$161,000–$194,000Middle half of postings
- Top 10%$194,000and above
- Postings9with a pay range
Posted base pay ranges from job listings, not total compensation. Figures are in USD. How these figures are made
Boeing’s ASIC/FPGA Design and Verification Engineer titles
Pay by level
Locations
- United States · $161K median · 9 postings
- New Mexico · $161K median · 4 postings
- Albuquerque, NM · $161K median · 4 postings
- California · 2 postings
- Mountain View, CA · 2 postings
Newest Boeing ASIC/FPGA Design and Verification Engineer postings
- ASIC/FPGA Design and Verification Engineer – Space Electronics – (Senior or Principal) - MTVBoeing · Mountain View, CA · $165K–$223K/yr · Posted Sep 27, 2026ApplyView posting
- ASIC/FPGA Design and Verification Engineer – Space Electronics – (Senior or Principal) - MTVBoeing · Mountain View, CA · $165K–$223K/yr · Posted Sep 27, 2026ApplyView posting
- ASIC/FPGA Design and Verification Engineer – Space Electronics – (Senior or Principal) - MTVBoeing · United States · $165K–$223K/yr · Posted Sep 26, 2026ApplyView posting
- ASIC/FPGA Design and Verification Engineer – Space Electronics – (Senior or Principal) - MTVBoeing · United States · $165K–$223K/yr · Posted Sep 26, 2026ApplyView posting
- ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal)Boeing · Albuquerque, NM · $137K–$185K/yr · Posted Aug 26, 2026ApplyView posting
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